Hardware acceleration in the form of customized datapath and control circuitry tuned to specific applications has gained popularity for its promise to utilize transistors more efficiently. Historically, the computer architecture community has focused on general-purpose processors and extensive research infrastructure has been developed to support research efforts in this domain, such as power-performance modeling and workload characterization. Envisioning future computing systems with a diverse set of general-purpose cores and accelerators, researchers must add accelerator-centric research infrastructures to their toolboxes to explore the future heterogeneous, accelerator-centric systems.
In this tutorial, we discuss state-of-the-art research infrastructures available for accelerator research ranging from applications to power-performance simulation to hardware prototyping. The first half of the tutorial will be focusing on modeling and simulation. We start the tutorial with Aladdin, a pre-RTL, power-performance simulator for fixed-function accelerators to help computer architects explore the design space of accelerators. We further introduce two complementary system-level simulation frameworks: gem5-aladdin, an integration of Aladdin and gem5 and PARADE, an integration of high-level synthesis and gem5, to study the interaction between accelerators and the rest of the system. To help designers understand workload intrinsic characteristics, we continue the tutorial with WIICA, an ISA-independent workload characterization tool for accelerators.
The second half of the tutorial focuses on applications and prototyping. We will present two accelerator benchmark suites: MachSuite and Medical Imaging Benchmarks, followed by a discussion on recent advances in high-level synthesis tools. We will introduce an FPGA prototype flow and evaluation framework for Accelerator-Rich Architectures (ARA). A live demo will be demonstrated using a Zync FPGA cluster at UCLA.
We will organize a panel to discuss the accelerator roadmap for the computer architecture community before the hands-on exercise. We will invite researchers from both industry and academia to discuss what we need to do to build a healthy ecosystem to enable ARA research.
Ameen Akel (Micron)
Chris Batten (Cornell)
Derek Chiou (UT-Austin/Microsoft)
Michael Kishinevsky (Intel)
Boris Ginzburg (Intel)
Prof. David Brooks,
Harvard University (email@example.com)
Yu-Ting Chen, UCLA (firstname.lastname@example.org)
Prof. Jason Cong, UCLA (email@example.com)
Zhenman Fang, UCLA (firstname.lastname@example.org)
Brandon Reagen, Harvard University (email@example.com)
Prof. Glenn Reinman, UCLA (firstname.lastname@example.org)
Yakun Sophia Shao, Harvard University (email@example.com)
Prof. Gu-Yeon Wei, Harvard University (firstname.lastname@example.org)
Sam Xi, Harvard University (email@example.com)
Aladdin: A pre-RTL, power-performance-area simulator for accelerators.
LLVM-Tracer: An LLVM optimization pass to print a dynamic LLVM IR trace.
MachSuite: A benchmark suite for accelerators.
WIICA: An ISA-independent workload characterization tool for accelerators.
Medical Imaging Pipeline: Tools and algorithms for developing an accelerated medical image processing pipeline.
International Conference on Computer Design (ICCD), Oct 2013.
Morgan & Claypool, July 2015.
International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2015.
International Conference on Computer-Aided Design (ICCAD) 2015, to appear.