Research Infrastructures for Accelerator-Centric Architectures

Full Day Tutorial: Sunday, June 15, 2014 at ISCA 2014

Hardware acceleration in the form of customized datapath and control circuitry tuned to specific applications has gained popularity for its promise to utilize transistors more efficiently. Historically, the computer architecture community has focused on general-purpose processors and extensive research infrastructure has been developed to support research efforts in this domain. Research infrastructure to study general-purpose computing designs is extensive, including analytical performance models, workload characterization approaches, detailed microarchitectural simulators, power/energy models, and design flows to enable architecture research. Envisioning future computing systems with a diverse set of general-purpose cores and accelerators, researchers must add accelerator-based research infrastructures to their toolboxes to be better equipped to explore the future heterogeneous, accelerator-centric systems.

In this tutorial, we discuss state-of-the-art research infrastructure available for accelerator computing research. The tutorial is split into post-RTL and pre-RTL modeling and design. We first discuss standard ASIC design flow from RTL generation, simulation, and synthesis. Recent advances in high-level synthesis (HLS) tools provide a promising path for accelerator development in the future, and we describe the capabilities of commercial tools like Xilinx's Vivado HLS. However, RTL flows are necessarily low-level and relying exclusively on such flows inhibits architectural research. The second half of the tutorial describes higher level modeling tools and techniques. We introduce an ISA-independent workload characterization approach to understand workload behavior before designing accelerators. Then we show a pre-RTL, power-performance simulation framework to facilitate architects rapidly explore the design space of accelerators. Finally, we discuss how analytical models can be constructed to guide resource allocation between general-purpose cores and accelerator designs.

Tutorial Outline


Tutorial Organizers

Prof. David Brooks, Harvard University (
Dr. Parimal Patel, Xilinx (
Brandon Reagen, Harvard University (
Yakun Sophia Shao, Harvard University (
Prof. Kevin Skadron, University of Virginia (
Liang Wang, University of Virginia (
Prof. Gu-Yeon Wei, Harvard University (


Quantifying Acceleration: Power/Performance Trade-Offs of Application Kernels in Hardware,
Brandon Reagen, Yakun Sophia Shao, Gu-Yeon Wei and David Brooks

International Symposium on Low Power Electronics and Design (ISLPED), Sept 2013. [PDF]

Aladdin: A Pre-RTL, Power-Performance Accelerator Simulator Enabling Large Design Space Exploration of Customized Architectures,
Yakun Sophia Shao, Brandon Reagen, Gu-Yeon Wei and David Brooks

International Symposium on Computer Architecture (ISCA), June 2014. [PDF]

ISA-Independent Workload Characterization and its Implications for Specialized Architectures,
Yakun Sophia Shao and David Brooks

International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2013. [PDF] [slides]

Implications of the Power Wall: Dim Cores and Reconfigurable Logic,
Liang Wang and Kevin Skadron

IEEE Micro, 2013 [PDF]