Aladdin and gem5-Aladdin:

Research Infrastructures for Specialized Architectures

Half Day Tutorial: Sunday Morning, September 25, 2016 at IISWC 2016

Hardware acceleration in the form of customized datapath and control circuitry tuned to specific applications has gained popularity for its promise to utilize transistors more efficiently. Historically, the computer architecture community has focused on general-purpose processors and extensive research infrastructure has been developed to support research efforts in this domain, such as power-performance modeling and workload characterization. Envisioning future heterogeneous, accelerator-centric computing systems with a diverse set of general-purpose cores and accelerators, researchers must add a set of new accelerator-centric research infrastructures to their toolboxes.

In this tutorial, we discuss state-of-the-art research infrastructures available for accelerator research ranging from power-performance simulation to hardware prototyping. We start the tutorial with Aladdin, a Pre-RTL, power-performance simulator for fixed-function accelerators to help computer architects explore the design space of accelerators. We further introduce a complementary system-level simulation framework: gem5-Aladdin, an integration of Aladdin and gem5, to study interactions between accelerators and the rest of the system. Finally, we will demonstrate the capabilities of the Zynq Zedboard platform, which combines a general-purpose ARM core with an FPGA over a coherent interconnect. Hands-on exercises and demo will be included to show how to use these tools to address different research questions.

Tutorial Outline


Tutorial Organizers

Prof. David Brooks, Harvard University (
Yakun Sophia Shao, NVIDIA Research (
Prof. Gu-Yeon Wei, Harvard University (
Sam Xi, Harvard University (

Software Download


Co-Designing Accelerators and SoC Interfaces using gem5-Aladdin
Yakun Sophia Shao, Sam Likun Xi, Viji Srinivasan, Gu-Yeon Wei and David Brooks

International Symposium on Microarchitecture (MICRO), Oct 2016. [PDF] [bibtex]

Toward Cache-Friendly Hardware Accelerators,
Yakun Sophia Shao, Sam Xi, Viji Srinivasan, Gu-Yeon Wei and David Brooks

HPCA Sensors and Cloud Architectures Workshop (SCAW), Feb 2015. [PDF] [slides] [bibtex]

MachSuite: Benchmarks for Accelerator Design and Customized Architectures,
Brandon Reagen, Bob Adolf, Yakun Sophia Shao, Gu-Yeon Wei and David Brooks

International Symposium on Workload Characterization (IISWC), October 2014. [PDF] [bibtex]

Aladdin: A Pre-RTL, Power-Performance Accelerator Simulator Enabling Large Design Space Exploration of Customized Architectures,
Yakun Sophia Shao, Brandon Reagen, Gu-Yeon Wei and David Brooks

International Symposium on Computer Architecture (ISCA), June 2014. [PDF] [slides] [bibtex]

Quantifying Acceleration: Power/Performance Trade-Offs of Application Kernels in Hardware,
Brandon Reagen, Yakun Sophia Shao, Gu-Yeon Wei and David Brooks

International Symposium on Low Power Electronics and Design (ISLPED), Sept 2013. [PDF] [bibtex]

ISA-Independent Workload Characterization and its Implications for Specialized Architectures,
Yakun Sophia Shao and David Brooks

International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2013. [PDF] [slides] [bibtex]