Research Infrastructures for Accelerator-Centric Architectures

Full Day Tutorial: Sunday, Feb 8th, 2015 at HPCA 2015

Hardware acceleration in the form of customized datapath and control circuitry tuned to specific applications has gained popularity for its promise to utilize transistors more efficiently. Historically, the computer architecture community has focused on general-purpose processors, and extensive research infrastructure has been developed to support research efforts in this domain, such as power-performance modeling and workload characterization. Envisioning future computing systems with a diverse set of general-purpose cores and accelerators, researchers must add accelerator-centric research infrastructures to their toolboxes to explore the future heterogeneous, accelerator-centric systems.

In this tutorial, we discuss state-of-the-art research infrastructure available for accelerator computing research ranging from applications to workload characterization to power-performance simulation. We start the tutorial with Aladdin, a pre-RTL, power-performance simulator for fixed-function accelerators to help computer architects explore the design space of accelerators. We further introduce the integration of Aladdin and gem5 for accelerators system-level simulation in order to study the interaction between accelerators and the rest of the system. We will also present an accelerator benchmark suite: MachSuite, followed by a discussion on recent advances in high-level synthesis tools.

We start the second part of the tutorial by an embedded keynote from Prof. Mark Horowitz (Stanford). We then focus the discussion on workload characterization. Two workload characterization tools will be presented: WIICA, an ISA-independent workload characterization approach, and Sigil, a platform-independent communication characterization tool. We will conclude this tutorial with a hands-on exercise session.

Slides


Tutorial Organizers


Prof. David Brooks, Harvard University (dbrooks@eecs.harvard.edu)
Prof. Mark Hempstead, Drexel University (mhempstead@coe.drexel.edu)
Mike Lui, Drexel University (mike.lui@drexel.edu)
Parnian Mokri, Drexel University (pm626@drexel.edu)
Siddharth Nilakantan, Drexel University (sn446@drexel.edu)
Brandon Reagen, Harvard University (reagen@fas.harvard.edu)
Yakun Sophia Shao, Harvard University (shao@eecs.harvard.edu)
Prof. Gu-Yeon Wei, Harvard University (guyeon@eecs.harvard.edu)

References


Platform-Independent Analysis of Function-Level Communication in Workloads,
Siddharth Nilakantan and Mark Hempstead

International Symposium on Workload Characterization (IISWC), Sept 2013.


Quantifying Acceleration: Power/Performance Trade-Offs of Application Kernels in Hardware,
Brandon Reagen, Yakun Sophia Shao, Gu-Yeon Wei and David Brooks

International Symposium on Low Power Electronics and Design (ISLPED), Sept 2013. [PDF]


MachSuite: Benchmarks for Accelerator Design and Customized Architectures,
Brandon Reagen, Bob Adolf, Yakun Sophia Shao, Gu-Yeon Wei and David Brooks

International Symposium on Workload Characterization (IISWC), October 2014. [PDF]


Aladdin: A Pre-RTL, Power-Performance Accelerator Simulator Enabling Large Design Space Exploration of Customized Architectures,
Yakun Sophia Shao, Brandon Reagen, Gu-Yeon Wei and David Brooks

International Symposium on Computer Architecture (ISCA), June 2014. [PDF] [slides]


ISA-Independent Workload Characterization and its Implications for Specialized Architectures,
Yakun Sophia Shao and David Brooks

International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2013. [PDF] [slides]