Hardware acceleration in the form of customized datapath and control circuitry tuned to specific applications has gained popularity for its promise to utilize transistors more efficiently. Historically, the computer architecture community has focused on general-purpose processors, and extensive research infrastructure has been developed to support research efforts in this domain, such as power-performance modeling and workload characterization. Envisioning future computing systems with a diverse set of general-purpose cores and accelerators, researchers must add accelerator-centric research infrastructures to their toolboxes to explore the future heterogeneous, accelerator-centric systems.

In this tutorial, we discuss state-of-the-art research infrastructure available for accelerator computing research ranging from applications to workload characterization to power-performance simulation. We start the tutorial with Aladdin, a pre-RTL, power-performance simulator for fixed-function accelerators to help computer architects explore the design space of accelerators. We further introduce the integration of Aladdin and gem5 for accelerators system-level simulation in order to study the interaction between accelerators and the rest of the system. We will also present an accelerator benchmark suite: MachSuite, followed by a discussion on recent advances in high-level synthesis tools.

We start the second part of the tutorial by an embedded keynote from Prof. Mark Horowitz (Stanford). We then focus the discussion on workload characterization. Two workload characterization tools will be presented: WIICA, an ISA-independent workload characterization approach, and Sigil, a platform-independent communication characterization tool. We will conclude this tutorial with a hands-on exercise session.

Tutorial Schedule